What People are Saying

"Tools alone aren’t enough to reduce dynamic and leakage power in complex chip designs – a wellplanned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe such a low-power methodology with a practical, step-by-step approach."

Richard Goering, Software Editor, EE Times

"Excellent compendium of low power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion."

Sujeeth Joseph, Chief Architect - Semiconductor & System Solutions Unit, Wipro Technologies

"The LPMM enables broader adoption of aggressive power management techniques. Based on extensive experience and silicon examples with real data, the LPMM provides methodology that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs."

Anil Mankar, Sr. VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems, Inc.

"Managing power at 90nm and below introduces significant challenges to the design flow. The LPMM is a timely and immediately useful book that shows how the combination of tools, IP, and methodology can be used together to address power management."

Nick Salter, Head of Chip Integration, CSR plc.

"LPMM is a great vehicle for the design community to learn and apply low power design techniques."

Ed Huijbregts, Ph.D., VP Product Development – Design Implementation, Magma Design Automation